Search found 7 matches
- 2022-12-03, 21:17:53
- Forum: forwardcom forum
- Topic: Integer division by zero
- Replies: 4
- Views: 31575
Re: Integer division by zero
Hello Mr Fog, I understand that the concept of processor flags is outdated and making superscalarity much harder to implement. But just as an idea, if your ISA concept had a single debug register to store the program counter of the failing calculation, wouldn't this mitigate the underlying problem? ...
- 2022-05-19, 0:23:56
- Forum: forwardcom forum
- Topic: Bit addressing
- Replies: 8
- Views: 43128
Re: Bit addressing
Hello Validark!, I would like to add to the discussion that I expect the ability of a general purpose CPU to interpret opcodes that are bit adressed unreasonable expensive to implement in an actual hardware design. Not only would it make the hardware more complex, It would make things slow. From a s...
- 2020-05-20, 16:36:22
- Forum: forwardcom forum
- Topic: Handshaking between CPU pipeline stages
- Replies: 6
- Views: 13091
Re: Handshaking between CPU pipeline stages
You can work around all these things if your dispatcher has a very good "bookkeeping". The challenge is to keep it simple while still dispatching as aggressive as possible. Some details will go hand in hand with your distinct definition of your ISA. The pipeline should be tailored for your...
- 2020-05-20, 12:04:52
- Forum: forwardcom forum
- Topic: Handshaking between CPU pipeline stages
- Replies: 6
- Views: 13091
Re: Handshaking between CPU pipeline stages
The big problem that might occur is that there will be memory violations. But in that event, you will want to stop the processing of the program anyway. If the reads are checked for their privilege before dispatching the instructions and the writes are checked for their privilege before leaving the ...
- 2020-05-19, 21:06:46
- Forum: forwardcom forum
- Topic: Separate call stack and data stack
- Replies: 6
- Views: 15315
Re: Separate call stack and data stack
What I like about the idea of a seperate call stack and data stack is, that parallel resources tend to be much faster than mixed purpose data on the same data track. Also to evade some issues of unsafe programming such a feature is more than useful. After all you will have to speficy some way it act...
- 2020-05-19, 19:50:43
- Forum: forwardcom forum
- Topic: Handshaking between CPU pipeline stages
- Replies: 6
- Views: 13091
Re: Handshaking between CPU pipeline stages
Hello Agner, I have never build a pipelined CPU nor a FPGA-Implementation of it, but to me it looks like the solution you are working on might put you into a situation where you end up with far too much synchronisation of the pipeline stages. In the end, you are prepared for many cornercases, but I ...
- 2020-04-17, 18:44:15
- Forum: forwardcom forum
- Topic: What about optimising for faster loops?
- Replies: 1
- Views: 8296
What about optimising for faster loops?
When there are relatively short code segments that are repeated many times, a lot of theoretical performance is not available. Depending on the exact architecture there are slowdowns after a jump. To unroll loops is a common attempt to raise performance in such cases. But in general this can have dr...