Heterogenous cores / instruction sets

[JoeDuarte]

Hi Agner – The implicit assumption of most ISAs, and of ForwardCom, is that all cores are the same and implement the same instructions. Why?

Would there be a benefit of having some cores be simpler, implementing a subset of the ISA? For example, does every core need to support floating point? Or wide SIMD floating point registers? Most applications don't actually use floating point arithmetic, so it's strange that all cores support it in conventional ISAs.

How much benefit would there be in cost and energy use if say four cores were integer-only, and another four cores supported the full instruction set? Threads that needed floating point would run on the appropriate cores. Encryption like AES-NI is another example. On client devices those instructions could easily be limited to one core with no relevant loss of performance, since the frequency of encryption/decryption events is trivial compared to the computational speed of those instructions.

Just a thought. You could have two types of cores. Or three.

[agner]

Yes, that would certainly be useful. Especially if the OS can know in advance whether a new process or a new thread needs the extra resources, so that it wouldn't have to jump to another core in case a thread has been started in a core that doesn't fit its needs.

[HubertLamontagne]

ARM is pretty good at this (obviously it has to, since so much of their business is embedded cores), with the whole gamut:

- Stripped down 32bit (modern small microcontrollers)
- 32bit (lots of microcontrollers and smaller cores, GBA and NDS)
- 32bit + FPU (used in some microcontrollers for DSP-heavy tasks like guitar effect pedals)
- 32bit + MMU (some early cell phones)
- 32bit + FPU + MMU (tons of android and iphone cell phones, beefier microcontrollers)
- 32bit + FPU + MMU + SIMD (tons of android and iphone cell phones, beefier microcontrollers)
- 64bit + FPU + MMU + SIMD (beefy modern ARM cores)

You can see roughly the same progression of features in other architectures, especially RISC-V, but also MIPS and x86. This is not just for chip-area and power-usage reasons, but also for complexity reasons since FPUs, MMUs and SIMD increase the complexity of the core so much.

For Forwardcom, I imagine that a cut-down version would lack the vector registers and instructions removed, right?

[agner]

I have started to make a softcore for an FPGA (Artix 7). In this early stage, I am using only on-chip RAM so I don't need 64 bit addresses. But integer registers should probably be 64 bits anyway for the sake of compatibility. I guess it will be configurable so that you can choose floating point support: half precision, single precision, double precision, all of these, or none. And of course you can choose the number of SIMD lanes.