Putting it on real hardware

[piegames]

I searched in this forum but couldn't find it: Has anyone already built a processor using this architecture for an FPGA (or even real ASIC)? Or is this purely theoretical until now?

[agner]

No, this is in a development stage. It has not been coded on an FPGA yet. Any help with this will be appreciated.

[piegames]

Are there any scientific papers on the ISA or on topics that are relevant to it?

[agner]

It is all on https://www.forwardcom.info and in the manual https://github.com/ForwardCom/manual/ra ... ardcom.pdf.
I think it is too early to write papers about it.

Forwardcom is currently a one man project and I am busy with other projects right now. That's why progress goes slowly. It would be nice if somebody else joins the project.

[HubertLamontagne]

You'd start with an in-order implementation in Verilog (or VHDL), I'd think, using block RAM instead of DRAM for instruction memory and data memory at first... and probably no vector support initially, and not too much pipelining at first. Then, you'd build up from there.

You'd presumably start with these operations:
nop, store, move, sign_extend, sign_extend_add, add, compare, sub, sub_rev, min, min_u, max, max_u, and, and_not, xor, or, etc...

then add the mul operations:
mul, mul_hi, mul_hi_u, mul_ex, mul_ex_u, etc...

Once that works, get the other operations, floating point, vectors, memory spaces etc working.

Does that make sense?

[agner]

Thanks for the advice. I think that https://opencores.org/ is the place to host the project and look for help. I am just too busy with other projects to start it up right now.

[agner]

I have finally allocated time to do an FPGA implementation of ForwardCom. Can you mention some good examples of softcores that I can use as a starting template?

[Dom324]

What about Western Digitals SweRV? https://github.com/chipsalliance/Cores-SweRV